搜索资源列表
FPGA
- 基于FPGA的正弦信号发生器,该程序是由VHDL语言编程而成。-FPGA-based sinusoidal signal generator, the program is made by the VHDL programming language.
singt2048
- 正弦波信号发生器 VHDL-Sine wave signal generator sine wave signal generator
waveform_generator
- VHDL语言编写的波形发生器程序,可以产生方波、三角波、正弦波、锯齿波等波形-Waveform generator written in VHDL program that can generate a square wave, triangle wave, sine wave, sawtooth wave, etc.
singt
- 在EP2C35上用VHDL语言编程实现的正弦波形发生器-VHDL language used in the EP2C35 programming on the sine wave generator
sin
- 基于VHDL硬件描述语言的正弦波利用Maxplus的仿真实例-VHDL hardware descr iption language based on the sine wave using the simulation Maxplus
sin
- 设计一个正弦信号发生器,用VHDL设计出同步寄存器、相位累加器等,正弦ROM查找表建议采用定制器件的方法完成,正弦ROM数据文件可以用C代码完成。-failed to translate
sin
- 基于vhdl的正弦信号发生器,经验证,可作为单独模块使用-The sine signal generator based on VHDL, experience card
func_generator
- 一种可调频率的正弦信号发生器的vhdl实现,含测试文件-An adjustable frequency sinusoidal signal generator vhdl implementation, including the test file
DDS
- dds实现正弦波vhdl dds宏功能模块 实现各种波形-sine vhdl dds dds achieve macro modules to achieve a variety of waveforms
singt
- 基于fpga的正弦信号发生器,VHDL语言写的-Based on fpga sinusoidal signal generator, VHDL language
jiyuVHDLshizhongchengxu
- 基于VHDL的时钟、正弦波和方波实验报告-VHDL-based clock, sine and square wave experiment report
dds
- DDS数字函数信号发生器,采用VHDL编写,可以产生正弦波、锯齿波、三角波信号,信号的频率和相位都可调。-DDS Digital Function Generator using VHDL write, you can produce sine, sawtooth, triangle wave signal, the signal s frequency and phase are adjustable.
ALTERA@FPGA@example
- 基于ALTERA的几个VHDL实例,如FPGA单片机,DDS的正弦信号发生器,FPGA视频监控-VHDL example:such as DDS Sine signal generator
dds
- 这是个基于dds的正弦波发生器的程序,用vhdl语言编写, 希望对大家有用。 -This is a sine wave generator based on dds program, using vhdl language, want to be useful.
DDS
- DDS的正弦函数源代码实现。VHDL的源代码-dds vhdl you undersand you you you must understand and 20 gou le ba
design
- 基于vhdl的dds发生器,精度可达到1Hz,包含正弦波,三角波,方波-DDS based on VHDL,display resolution 1Hz, include sine wave,triangular wave, square wave
sinx
- 完整的正弦波频率产生,详细的源程序以及完整仿真,对学习vhdl及eda很有帮助,在modelsim中仿真-Complete sine wave frequency generator
singen
- 利用vhdl在quartusii中编写的正弦信号发生器,并在quartusii中进行了仿真-Using the VHDL in a QuartusII in the preparation of the sinusoidal signal generator, and makes simulation in QuartusII
fsk_tz
- vhdl实现FSK调制,本次毕业设计的数据速率 1.2kb/s,要求产生一个1.2kHz的正弦信号,对正弦信号每周期取100个采样点,因此要求产生3个时钟信号:1.2kHz(数据速率)、120kHz(产生1.2kHz正弦信号的输入时钟)、240kHz(产生2.4kHz正弦信号的输入时钟)。基准时钟已由一个外部时钟120MHz提供,要得到前面三种时钟,就需要首先设计一个模50的分频器产生240kHz信号,再设计一个二分频器,生产一个120kHz的信号,然后再前面的基础上再设计一个模100的分频器,
zheng_xian_bo
- 用Quartus II 9.0 产生正弦波的VHDL源代码。-Quartus II 9.0 VHDL source code of the sine wave.